Digital Designer

Ceva is at the forefront of the Smart Edge revolution, with innovative state-of-the-art Silicon and Software solutions that enable products to Connect, Sense and Infer.

Within the Wireless Internet of Things Business Unit (WIoT BU), we are offering you a unique opportunity to shape the future of connected devices. Our advanced wireless technologies, including Bluetooth, Wi-Fi UWB, and 5G Cellular IoT, are integrated into over a Billion devices annually.

About the Role:

In this role you will join the Wi-Fi design team, focusing on the development of next generation Wi-Fi technology. 

We are seeking a skilled digital Engineer, focused on RTL development of modules and sub-systems for Digital Signal Processing (DSP) and Wireless Communication applications.

The ideal candidate will show proficiency in Verilog and ASIC design flow for complex fixed-point applications; he/she will work within an ASIC design team to improve and develop modules of wireless IP that will be implemented in larger SoCs or ASICs.

He/She will work with digital architects, algorithm and verification experts to generate state-of-the-art solutions through efficient and high-quality code. He/She will be capable of analyzing design trade-offs and ensure functionality of implemented circuit against available model and support verification activities. He/She will be able to work in autonomy and capable of generating technical documentation.

 Key Responsibilities:

Update and design module starting from architecture specifications and ensure functionality against the reference model. Write efficient, high-quality RTL code in Verilog. Support functional verification activities by debugging failing tests in autonomy. Analyze problems and work with architects and algorithm experts to identity resolution and design trade-offs. Use Synopsys Design Compiler to run module level or top synthesis, analyze reports, resolve issues and identify trade-offs for area/power optimization. Use Synopsys Spyglass to assess and improve code quality. Support debug and validation of module functionality on prototyping platforms on FPGA. Write technical documentation describing micro-architecture, interfaces and module level testing.

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/FPGA design.
• Proficiency in Verilog and System Verilog.
• Proficiency in scripting (Shell, TCL).
• Proficiency with development under version control.
• Excellent analytical and problem-solving skills and capable of working in autonomy.
• Understanding of ASIC synthesis using DC Compiler.
• Good communication skills and excellent English

 Advantages:

• Experience with Matlab.
• Experience with FPGA flow on AMD/Xilinx toolchain.
• Experience with wireless communication protocols and application (WLAN, Bluetooth, UWB, Celluar etc.)
• Exposure to SVN version control.